INTRODUCING THE DATCUBE 82
POWER FOR THE FUTURE · AUSTIN, TEXAS · 1982
DC-82/1 · SER. NO. 0001 · QC-1 @ 4.8 MHz · DCIS-2 ISA
Technical Specifications
Built for Research.
Born to Compute.
CPU
Processor
QC-1 Quantum Core 1
Custom 16-bit CISC processor running at 4.8 MHz. 8 general-purpose 16-bit registers (R0–R5, MX, SX). Hardware-accelerated multiply/divide. Full IRQ support with 8 priority vectors.
ISA
Instruction Set
DCIS-2 · 42 Opcodes
DatCube Instruction Set version 2. Variable-length encoding, 3-bit register fields. Native coprocessor instructions for M3D mesh rendering and Sound DSP. Hardware segment selector register (SEG, 3-bit).
RAM
Memory
4 × 64 KB Internal
+ 1 MB Expansion
4 internal "Quantum RAM" segments (SEG 0–3). Expansion slot provides up to 16 × 64 KB pages (SEG 4–7), page-mapped at runtime via I/O registers. DMA controller for segment-to-segment block transfers.
VID
Video
512 × 288 · 60 Hz
5-Layer Compositor
16:9 progressive scan. Layer 0: 24-bit RGB copper-bar fill (per-scanline HBL IRQ). Layers 1–4: freely compositable text or pixel layers, 1/2/4/8bpp palette, Z-order assignable, split-screen via row skip/count.
M3D
3D Coprocessor
M3D · DMA Triangle Fill
Hardware vertex mesh renderer. Vertex format: 3 × s16 (X/Y/Z). Face format: 3 × u16 indices + u8 palette colour. Modes: wireframe, flat-shaded fill, Z-buffered fill. Accessed via MLOAD / MXFR / MREND instructions. IRQ5 on completion.
SND
Sound DSP
4-Channel + PCM DMA
4 synthesis channels: square, triangle, sawtooth, noise. Full ADSR envelope per channel. PCM streaming via DMA: once, loop, or ping-pong. Configured via STON / SENV / STOF instructions and I/O ports 0x30–0x39.
42 Opcodes
320 KB Internal RAM
5 Video Layers
4 Sound Channels
8 IRQ Vectors
42 Instructions.
Zero Compromises.

System

NOP0x00No operation
HLT0x01Halt processor, set H flag
INT0x02Software interrupt #n
RTI0x03Return from interrupt
EI0x04Enable interrupts (set I flag)
DI0x05Disable interrupts

Load / Store

LDI0x10Load 16-bit immediate into Rd
LDR0x11Load word from absolute address
LDX0x12Load word, register + offset
STR0x13Store word to absolute address
STX0x14Store word, register + offset
MOV0x15Register to register copy
LDB0x16Load byte (zero-extended)
STB0x17Store low byte of register

Arithmetic

ADD0x20Rd = Rs + Rt (sets C, V, N, Z)
SUB0x21Rd = Rs − Rt (sets C, V, N, Z)
MUL0x22Rd:Rd+1 = Rs × Rt (32-bit product)
DIV0x23Rd = Rs ÷ Rt; NMI on div/0
MOD0x24Rd = Rs mod Rt
ADDI0x25Rd = Rs + 8-bit immediate
SUBI0x26Rd = Rs − 8-bit immediate
INC0x27Rd++
DEC0x28Rd−−
NEG0x29Rd = −Rd (two's complement)

Logic & Shift

AND0x30Rd = Rs AND Rt
OR0x31Rd = Rs OR Rt
XOR0x32Rd = Rs XOR Rt
NOT0x33Rd = NOT Rs (bitwise)
SHL0x34Rd = Rs « n (sets C on overflow)
SHR0x35Rd = Rs » n (logical)
ASR0x36Rd = Rs » n (arithmetic, sign-ext)

M3D Coprocessor

MLOAD0x37DMA vertex array; MX ← vtx count
MXFR0x38Set transform: rot/scale/translate/fov
MREND0x39Render mesh → target seg; IRQ5 on done

Compare & Test

CMP0x40Set flags for Rs − Rt (no store)
CMPI0x41Set flags for Rs − 16-bit immediate
TEST0x42Set N/Z for Rs AND Rt (no store)

Sound Coprocessor

STON0x43Fire channel: freq, wave, vol; SX ← cfg
STOF0x55Stop channel #n immediately
SENV0x56Set ADSR from MX (att|dec) / SX (sus|rel)

Branch & Call

JMP0x50Unconditional jump (absolute)
JEQ0x51Jump if Z set
JNE0x52Jump if Z clear
JLT0x53Jump if N ≠ V
JGT0x54Jump if Z clear and N = V
JSR0x57Jump to subroutine (push PC)
RET0x58Return from subroutine (pop PC)
JMPR0x59Jump to address in register
JC0x5AJump if carry set
JNC0x5BJump if carry clear

Video & Sync

VPIX0x5CPlot pixel: R0=X R1=Y R2=colour
SYNC0x5DStall until coprocessor mask idle

Stack

PUSH0x60Push register onto stack
POP0x61Pop from stack into register
PUSHI0x62Push 16-bit immediate
PUSHA0x63Push all registers + SR
POPA0x64Pop all registers + SR

Segment & I/O

SEL0x70Set active data segment (0–7)
SREAD0x71Read word from explicit segment
SWRITE0x72Write word to explicit segment
SREADR0x73SREAD with register address
SWRITER0x74SWRITE with register address
OUT0x80Write register to I/O port
IN0x81Read I/O port into register
OUTI0x82Write 16-bit immediate to I/O port
Dat Sys Computer Inc.
Austin, Texas · 1976–1985
1976
Founded in a Garage on Barton Hills Drive
Three electrical engineers — Harold "Hal" Datten, Roy Systemski, and Evelyn Morse — pooled $18,000 in savings to found Dat Sys Data Systems in a rented garage in south Austin. Their initial focus was custom memory controllers for university mainframe systems. Hal had previously worked at Texas Instruments; Roy and Evelyn met at UT Austin's Electrical Engineering department.
1979
The QC-1 Chip: A Secret Project Begins
After landing a contract with the Southwest Research Institute to build a custom data-acquisition workstation, the team began secretly developing their own 16-bit processor — the QC-1, or "Quantum Core 1" (clocked at 4.8 MHz). The name was partly ironic: the chip had nothing to do with quantum physics. Hal simply liked the sound of it. Tape-out was completed in late 1979 using a process node licensed from Motorola.
1981
DCIS-2 ISA Finalised; First Prototype Boot
After eighteen months of revision, the DatCube Instruction Set v2 was frozen. The team discarded an earlier RISC-influenced design after benchmarking showed that the denser variable-length encoding of DCIS-2 gave better real-world throughput on their target workloads — scientific visualisation and signal processing. On April 3rd, 1981, the first QC-1 prototype board successfully booted to a command prompt. Roy reportedly cried.
1982
The DatCube 82 Ships to Research Institutions
Priced at $176,500 USD (roughly $590,000 in 2025 dollars), the DatCube 82 was never intended for the consumer market. Units shipped exclusively to research institutions, government laboratories, and select university departments. Fewer than 200 units were ever built. The machine featured the QC-1 processor, 320 KB of internal RAM, a custom 5-layer video compositor capable of 512×288 resolution at 60 Hz, a 3D mesh coprocessor, and a 4-channel sound DSP — a combination that would not appear in any consumer machine for nearly a decade.
1984
The DC-84 Project and the IBM Pivot
Plans for a follow-up machine — the DC-84, featuring a revised QC-2 processor at 10 MHz and 2 MB of base RAM — were shelved when Dat Sys Computer Inc. received a lucrative offer from IBM to license the DMA architecture underlying the M3D coprocessor for use in high-end IBM workstations. The company quietly pivoted to semiconductor IP licensing. The Austin office was closed; Evelyn Morse relocated to Palo Alto to lead the new IBM partnership.
1985
Dissolution
With the IBM licensing deal complete and the consumer PC market consolidating rapidly around x86 architectures, Hal Datten officially dissolved Dat Sys Computer Inc. in March 1985. Roy Systemski went on to co-found a CAD software company in Dallas. The original QC-1 chip design documents and DCIS-2 specification were donated to the Computer History Museum in 2003. As of today, fewer than 12 known functioning DatCube 82 units remain in existence — most in private collections.
$176,500
Original List Price · 1982 USD Approximately $590,000 in 2025 dollars.
Distribution: research institutions only. No retail sales.
Total units produced: est. 194 · Units surviving: est. 12